The present invention is relevant to NOR flash memory devices, in particular to programming data into the NOR flash memory devices.
Flash memory devices are usually classified into NAND and NOR types. The NAND flash memory device has a structure of strings, in which a plurality of memory cells is connected from a single bitline in series. On the other side, the NOR flash memory device is constructed of a plurality of memory cells connected to a single bitline in parallel.
FIG. 1 shows a section of a memory cell employed in a flash memory device. As illustrated in FIG.1, a flash memory cell is composed of a source region 3 and a drain region 4 that are formed in a P-type substrate 9, a floating gate 6 formed over a channel region with an interposing thin insulation film 5 less than 100 Å therebetween, and a control gate 8 formed over the floating gate 6 with an interposing insulation film (an ONO film) 7. In FIG. 1, the source region 3, the drain region 4, the control gate 8, and the substrate 9 are connected to voltages Vs, Vd, Vg, and Vb, respectively.
FIG. 2 illustrates a cell bias condition in programming a memory cell of a NOR flash memory device. In a program operation, the source region 3 and the substrate 9 are grounded. The control gate 8 is connected to a high voltage of about 10V, while the drain region 4 is connected to a voltage of about 5V. With this bias condition, electrons are injected into the floating gate 6 from a channel region adjacent to the drain region 4 as shown in FIG. 2A. Such a mechanism, called channel hot electron injection, programs a memory cell in a different way from the method of F-N (Fouler-Nordheim) tunneling. By the program operation, the floating gate 6 is set to a negative potential, which acts to increase the threshold voltage of the memory cell during a read operation. A memory cell with this state is referred to as “off cell”.
Generally, as illustrated in FIG. 2B, when a voltage of about 5V is applied to the drain region 4 of a memory cell during a program operation, a cell current of about 200 μA flows from the drain region 4 towards the grounded source region 3 by way of the channel region. For instance, simultaneously programming data bits of a unit byte/word requires a current of 1.6 mA (200 μA×8) maximum for the unit byte, while a current of 3.2 mA (200 μA×16) maximum for the unit word.
As such, the NOR flash memory device needs to supply a cell current flowing through a memory cell and a voltage of about 5V to a bitline during a program operation. For this purpose, the NOR flash memory device usually employs an internal charge pump circuit. However, it is inevitable to have a limit in the number of bits programmable in a given time because such a charge pump circuit occupies a large circuit area.
Generally, the NOR flash memory device is programmed in units of bytes (8 bits) or words (16 bits). It is required to shorten the program time per unit byte or unit word when a multiplicity of NOR flash memory devices is necessary to be programmed with predetermined data (e.g., system operation codes). Further, according to trends, increased memory capacity leads to an overall increase of time to program the entire memory cells. Thus a reduction of program time will be more important as an actual factor in improving operational performance.